1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a semiconductor memory including NOR type cells in which memory cell transistors are located between adjacent bit lines and virtual ground lines.
2. Description of Related Art
In the prior art, the NOR type memory cells have been well known, which are used as memory cells for a large-capacity, high-speed mask read only memory (ROM), and in which memory cell transistors are located between adjacent bit lines and virtual ground (GND) lines, and word lines are located orthogonal to the bit lines and virtual GND lines.
FIG. 1 is a view illustrating the construction of one example of the prior art semiconductor memory using the above mentioned NOR type memory cells. In this drawing, this prior art semiconductor memory is mainly constituted of a NOR type cell array formed of memory cell transistors M01 to Mn8, a selection circuit 1, a precharge circuit 2, a sense amplifier 3, a selection circuit 4, a precharge circuit 5, and virtual GND lines.
In addition, this semiconductor memory includes bit lines and virtual GND lines D1 to D9, word lines WD0 to WDn, bit line selecting transistors S11 to S16, virtual GND line selecting transistors S20 to S26, bit line selecting lines BS0 and BS1, and virtual GND line selecting lines BS2 and BS3.
In the NOR type cells, one block from the bit line selecting transistors S11 to S16 to the virtual GND line selecting transistors S20 to S26, is called one bank, and when one memory cell is selected, one word line in the one bank is brought to a VCC level. Since the selected word line WDk (where "k" is any one of 0 to n) brought to the VCC level is connected to gates of a plurality of (in this example, eight) memory cell transistors Mk1 to Mk8, when the selected cell transistor is an off-cell and an adjacent non-selected cell transistor is an on-cell, a current flows through the selection circuit 1 from the sense amplifier 3 flows through the non-selected cell transistor, with the result that it is deemed as if the on-cell were read out.
In order to prevent this erroneous operation, the system has been conventionally adopted in which the non-selected bit line and the non-selected GND line are connected to the precharge circuits 2 and 5 by the selection circuits 1 and 4, respectively, so that the those lines are brought to the same level as those of the selected bit line, with the result that no current flows from the sense amplifier 3 to the non-selected cell transistor.
Here, assuming that both of the selected memory cell transistor and the non-selected memory cell transistor adjacent to the selected memory cell transistor are on-cells, the operation of the circuit shown in FIG. 1 will be described.
In the case of reading out the memory cell transistor M05 in FIG. 1, the word line WD0, the bit line selecting line BS0 and the virtual GND line selecting line BS3 are pulled up to the VCC level. On the other hand, the bit line selecting line BS1 and the virtual GND line selecting line BS2 are brought to the GND level. At this time, by the selection circuit 1, a bit line Y1 is connected to the precharge circuit 2 and a bit line Y2 is connected to the sense amplifier 3. In addition, by the selection circuit 4, the virtual GND lines VG1 and VG3 are connected to the precharge line 5 and the virtual GND line VG2 is connected to the virtual GND.
Accordingly, as the bit line, D6 is selected which is connected to the bit line Y2 through the turned-on bit line selecting transistor S14, and as the virtual GND line, D5 is selected which is connected to the virtual GND line VG2 through the turned-on virtual GND line selecting transistor S23. Thus, it can be put in a condition of selecting the memory cell transistor M05 having a drain and a source connected to the bit line D6 and the virtual GND line D5, respectively.
In the prior art, in addition, a semiconductor memory is known, which is intended to prevent a current from flowing to the bit line and virtual GND line from the direction of the word line side (Japanese Patent Application Pre-examination Publication No. JP-A-6-68683). This prior art semiconductor memory is constructed as shown in a constructive view of FIG. 2. Memory cell transistors are connected to bit lines 11 to 14 and virtual GND lines 15 to 19 in the form of an array, and metal bit lines 31, 32 and 33 are provided each one for each two bit lines and in common to a plurality of blocks. These metal bit lines are connected to precharge circuits including transistors 41, 42 and 43 between a Y gate circuit 25 and the memory cell array.
In addition, metal virtual GND lines 51 and 52 are provided each one for each two adjacent virtual GND lines, and are connected to precharge circuits 26 and 27, respectively. Furthermore, Reference Numerals 20 and 21 designate a bit line selecting line, and Reference Numerals 22 and 23 denote virtual GND line selecting line. Reference Numeral 24 indicates a word line.
In this prior art semiconductor memory, when a memory cell transistor 101 is read out, the word line 24, the virtual GND line selecting line 22 and the bit line selecting line 20 are pulled up to the VCC level. On the other hand, the virtual GND line selecting line 23 and the bit line selecting line 21 is brought to the GND level. In this condition, only the metal virtual GND line 51 is brought to the GND level, and the other metal virtual GND lines are brought to a precharge level.
Thus, the virtual GND line 16 and 17 are brought to the GND level and the other virtual GND lines 15, 18 and 19 are brought to the precharge level. The bit line 32 is selected by the Y gate circuit 25. Since the bit line selecting line 20 is at the VCC level and the bit line selecting line 21 is at the GND level, the transistor 103 is turned off and the transistor 104 is turned on. Therefore, it is put in a condition in which the bit line 13 is selected to be connected through the transistor 104 to the metal bit line 32. Thus, the memory cell transistor 101 is put in a selected condition.
However, in the prior art semiconductor memory shown in FIG. 1, when both the selected cell transistor Mk1-Mk8 connected to the selected word line WDk, and the adjacent non-selected cell transistor are the on-cell, the current flows from the sense amplifier 3 and the current flows from the precharge circuit 2 flow together into the virtual GND line in common to the two cell transistors, with the result that the current flows from the sense amplifier is reduced, and therefore, a problem is encountered that there is possibility that it is erroneously judged as if the off-cell were read out.
For example, considering the case that the above mentioned memory cell transistor M05 is selected, the lines D6 and D5 are selected as the bit line and the virtual GND line, respectively. At this time, since the bit line D4 is precharged from the precharge circuit 2 through the bit line Y1 and the turned-on bit line selecting transistor S13, a current simultaneously flows to the selected virtual GND line D5 through the non-selected memory cell transistor M04 adjacent to the selected memory cell transistor M05. Therefore, the current flowing into the selected memory cell transistor M05 from the sense amplifier 3 is reduced, with the result that the memory cell transistor M05 is judged as the off-cell.
Furthermore, in the prior art semiconductor memory shown in FIG. 2, since the virtual GND line of the non-selected memory cell transistor adjacent to the selected memory cell transistor is precharged, when the non-selected memory cell transistor is an on-cell, a current flow directly into the selected bit line.
For example, considering that the above mentioned memory cell transistor 101 is selected, when the adjacent non-selected memory cell transistor 102 is an on-cell, since the virtual GND line 18 is at the precharge level, the current flows directly into the bit line 13. As a result, the current flowing from the metal bit line 32 is reduced, so that a problem is encountered that there is possibility that although the memory cell transistor 101 is an on-cell, it is erroneously judged as it were the off-cell.